Alcyone LDPC
General Description

EpoStar’s LDPC IP Core (Alcyone) delivers industry-leading error correction performance to support 2S/3D SLC/MLC/TLC/QLC NAND for each application from mobile, client, and enterprise NAND flash controller markets. Alcyone provides a high efficient pure hardware engine with standard AXI interface for easily integration.

Based on several patented technology of EpoStar, the Alcyone LDPC IP provides very high throughput and error correction capability with low area and power consumption.

EpoStar’s LDPC IP was silicon-proven in industrial/enterprise SSD, USB, and EMMC application.

Key Features

+Support 1KB+/2KB+/4KB+ codeword size for one time configuration
+Support configurable throughput, up to 8GB/s
+Support hard-bit decode (HBD) and soft-bit decode (SBD)
+Proven to reach UBER lower than 1E-17 in both HBD and SBD
+Build in low power engine
+Support up to 6bit SBD
+Support variable code rate for various 2D/3D SLC/MLC/TLC/QLC NAND flash
+Support byte-by-byte adjustment in user data and parity data area of code rate
+Support on-the-fly dynamic code rate swapping
+Support on-the-fly bit error rate monitoring
+Support out-of-order decoding
+Support configurable termination condition
+Qualified with AWGN channel model platform and real NAND flash platform

Functional Block Diagram
      +LDPC Encoder
      +LDPC Decoder
UBER Performance with TLC code rate

+RTL code
+Sanity check RTL simulation environment
+Synthesis script for ASIC and FPGA
+LDPC encoding/decoding C library
+LDPC encoding/decoding matrices
+NAND flash LLR LUT calibration utility
+Training Course