Alcyone LDPC
General Description

EpoStar’s LDPC IP Core (Alcyone) incorporates dynamic variable code rates (DVCR) technology and delivers industry-leading error correction performance to enable 1x/1y/1z TLC for both enterprise and client SSD markets. The DVCR technology allows SSD design to apply different code rates according to the characteristics of NAND flash, and can extend the SSD life cycles up to 3 times without any read/write performance degradation compared to traditional SSD technologies. It can also expand the SSD capacity or reduce the BOM cost under the same warranty requirement. With EpoStar’s patented low-complexity LDPC architecture, Alcyone solves the area and power consumption problems that LDPC designs usually have, and enables low-power and cost-effective SSD controllers. Alcyone is delivered with a complete development package for the ease of use in both FPGA and SoC design.

Key Features

+Dynamic variable code rates (DVCR)
     Single design for all code rates and various NAND specs
+Design for high error correction capability and very low error-floor
     Proven to reach UBER as low as 10E-17
+Support hard-bit decode (HBD) and soft-bit decode (SBD)
     No need for BCH outer code
     Proved on 1x/1y/1z MLC/TLC NAND flash
+Optimized architecture for high throughput with low gate count, and low power consumption
+Early termination for low power
+Build-in DSP functions
     NAND flash channel calibration
     Self-aware NAND flash statistic
     Intelligent soft information adjustment
+Powerful LDPC analysis FPGA suite
     AWGN channel model
     Reliable LDPC qualification system
+Automatic statistic collection system

Functional Block Diagram

+RTL code for both ASIC and FPGA
+Verilog direct test verification environment
+Synthesis script for Synopsys Design Compiler and Xilinx FPGA
+C models for LDPC encoder and decoder
+H matrix customized for customers’ requirements
     Integration guide
     Verification guide
     User guide