Meissa NVMe
General Description
EpoStar’s NVMe IP Core (Meissa) is compliant with NVM Express 1.3 specification and targets for both enterprise and client SSD markets. It is a highly hardware automated design that requires minimum software involvement from the CPU. It supports out-of-order IO Read data transfer and PRP pre-fetch which can boost the IOPS performance and minimize the Read latency. The end-to-end data protection and error handling mechanism of Meissa enable robust and reliable SSD products. Meissa is highly flexible and can be configured to fit in requirements of different applications. Meissa is delivered with a complete development package for the ease of use in both FPGA and SoC integration.
Key Features

Compliant to NVMe 1.3
+Support SRIOV
+Support multiple namespaces
+Support dual ports
+Support up to 128 submission queues
+Support up to 128 completion queues
+Support up to 512 outstanding commands
+Weighted round robin with urgent priority class command arbitration
+Support PRP IO command sets
+Support E2E data and control path protection
+Maximum memory page size of 64KB
+Minimum memory page size of 4KB
+Support physically contiguous or non-contiguous submission queues and completion queues
+Support MSI, MSI-X, and legacy interrupt
+Support interrupt coalescing
+Support LBA size 512B, 4096B
+Support Host Memory Buffer
+Pass UNH-IOL compliance test

Functional Block Diagram

RTL code for both ASIC and FPGA
+Verilog direct test verification environment
+Optional UVM verification environment
+Synthesis script for Synopsys Design Compiler and Xilinx FPGA
+NVMe reference firmware

     Integration guide
     Register specification
     Firmware programming guide